With recent increase in demands for electronic equipment, especially cell phones (including smartphones), portable music players, digital cameras, and tablet terminals, for example, a demand for nonvolatile semiconductor memory devices has increased, and techniques for achieving higher capacity, smaller size, higher speeds in writing and reading, and operation at lower power consumption have been actively developed.
Flash memories are currently the mainstream of nonvolatile memories, but rewriting in a flash memory takes time on the order of microseconds or milliseconds. Thus, improvement in performance of set equipment including the flash memory is inhibited.
In recent years, new nonvolatile memories that enable rewriting at higher speed with lower power consumption than flash memories have been actively developed. Examples of such new nonvolatile memories include resistive random access memories (ReRAMs) using variable resistance elements for memory devices. The resistive random access memory enables high-speed rewriting on the order of nanoseconds. In addition, the resistive random access memory requires only about 1.8 V for rewriting although a flash memory requires 10 V or higher. Thus, power consumption of nonvolatile memories can be reduced.
Patent Document 1 describes a configuration of a readout circuit of a resistive random access memory. Memory cells of the resistive random access memory are constituted by serially connected variable resistance elements and cell transistors. A variable resistance element stores data by setting the resistance of the variable resistance element at a high level or a low level in the range from 1 KΩ to 1 MΩ, for example, depending on stored data (data “0” or data “1”). Specifically, by utilizing a phenomenon in which the amount of memory cell current is large when the resistance of the variable resistance element is low, and is small when the resistance of the variable resistance element is high, the difference between these memory cell currents is detected by a sense amplifier circuit in a readout operation, thereby reading data stored in a memory cell.
A memory cell array in which memory cells described above are arranged in columns and rows includes a plurality of bit lines connected in common to variable resistance elements included in memory cells associated with the columns and also includes a plurality of source lines connected in common to source terminals of cell transistors included in the memory cells associated with the rows. In reading data, one of the bit lines or the source lines are input to the sense amplifier circuit and the other are grounded so that the bit lines and the source lines are charged. In this manner, the difference between the memory cell current values of the memory cell can be detected by the sense amplifier circuit, thereby enabling reading of data stored in the memory cells.
Patent Document 2 describes a configuration of a write circuit for a resistive random access memory. A memory cell of the resistive random access memory is constituted by a variable resistance element and a cell transistor that are serially connected. The variable resistance element can be set in a high resistance state or a low resistance state depending on the direction of a write voltage. Specifically, the memory cell can be set in a high resistance state by applying a write voltage to a variable resistance element side of the memory cell and grounding a cell transistor side of the memory cell. On the other hand, the memory cell can be set in a low resistance state by grounding the variable resistance element side of the memory cell and applying a write voltage to the cell transistor side of the memory cell.